The present invention relates to integrated circuits, and more specifically, to an arrangement of an integrated circuit with testing inputs.
Many integrated circuit chips include specialized test patterns and test logic structures that are used to verify internal chip logic circuits. The test patterns are used in a “testing mode” and the structures are controlled by chip test input/output (I/O) pins also known as c4s. In many VLSI chips, c4s are designed to be “bi-directional”, meaning they support a path into the chip, as well as a path out of the chip. Each c4 may be configured as an input OR an output (not both), depending on the desired function for each c4 by “personalizing” the c4 using hard wired tie values (tie to ‘1’ or tie to ‘0’) when the chip is designed. The value of the tie enables only the direction (into or out of the chip) the c4 is intended to be used in this chip application. The reverse path is disabled.
In testing, the internal latch and array states are assumed to be unknown or indeterminate at the start of testing. Because of the unknown state of latches in the chip at the beginning of a test, the chips are typically designed such that no latches are disposed between a c4 pin and the test logic structures. An un-initialized latch in the path between a c4 pin and the test logic structures could render the chip untestable.
The designed packaging constraints of chips often limit the number of dedicated test c4 pins that are fabricated on the chip. Shared test I/Os may be used to conserve space on a chip. The shared test I/Os are pins that function as a c4 testing pin during a testing mode, and as mainline function pins during mainline chip functions (non-testing or normal chip operation modes). The use of shared test I/Os may result in logic paths from the shared test I/Os that include undesirable logic loops. The undesirable logic loops create the potential for fundamental logic design rules to be broken.